This patent application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 60/385,478 filed on Jun. 3, 2002.
When a computer system is turned on, the basic input-output system (“BIOS”) image located in the non-volatile memory starts up the computer. As part of the start-up process, the BIOS typically checks that the computer components are operational, locates the boot program for loading the operating system, and passes control of the computer to the operating system once the operating system files have been loaded.
More than one BIOS image may be stored by the computer system. For example, in order to improve the reliability of the computer system, an earlier version of the BIOS image may be maintained as a backup. The earlier version can be for example the version from manufacture or the version from the last BIOS update. As another example, one of the stored BIOS images may include extra features which only need to be performed for certain start ups of the computer. When more than one BIOS image is stored, one of the stored BIOS images is selected for starting up the computer system.
FIG. 1 illustrates a prior art computer system 100. A bus 118 couples a central processing unit (“CPU”) 108, a server input/output (“ServerIO”) 150 and a baseboard management controller (“BMC”) 140. BMC 140 is typically on a separate chip than ServerIO 150, however a single chip for ServerIO 150 and BMC 140 is also feasible. CPU 108 is coupled through a north bridge 102 to a system memory 104 (RAM and/or ROM) and a GFX controller 106. A south bridge 110 and a bus 107 couple bus 118 and north bridge 102. An external bus (“X-bus”) 124 couples a flash A 120, a flash B 122 and ServerIO 150. Herein below, bus 118 is assumed to be a low pin count bus (“LPC”) and bus 107 is assumed to be a PCI bus, however other buses can be substituted. Included in flash A 120 is one of the BIOS versions and included in flash B 122 is the other BIOS version. Included in BMC 140 is a nonvolatile memory 142. Included in ServerIO 150 are an internal bus 152 and a flash selection module 153. Flash selection module 153 includes two registers 156 and 154 which are controlled by CPU 108 and enable chip select A 130 and chip select B 132 respectively.
In one example of operation, CPU 108 causes either control register 154 or control register 156 to be reset. If control register 156 is reset, then chip select A (“CSA”) 130 is asserted and the BIOS in Flash A 120 is accessed. If control register 154 is reset, then chip select B (“CSB”) is asserted and the BIOS in Flash B 122 is accessed. Once the desired flash is selected, CPU 108 selects addresses within the BIOS image of the selected flash via ServerIO 150 and X-Bus 124.
A limitation of system 100 relates to the control of the BIOS selection solely by CPU 108. If the CPU 108 is not able to control the selection when the active BIOS needs be changed for the other BIOS, the required changeover will not occur. CPU 108 may not be able to control the selection, for example if the active BIOS is damaged and CPU 108 can not begin running commands from the BIOS.
FIG. 2 shows an alternative prior art system 200, using memory management. The two BIOS images are stored in one flash 220. In operation, BMC 140 controls the selection of the BIOS image through address line (Ax) 244. Refer to FIG. 3. From the point of view of CPU 108, system memory 104 and flash memory 220 are accessible memory. BIOS image A or B, selected by Ax 244 is placed in the top position. In FIG. 3, the unbroken lines represent the case when BIOS image A 320 was the BIOS selected and the broken lines represent the instance when BIOS image B 322 was the BIOS selected. Once the desired BIOS image has been selected, CPU 108 through ServerIO 250 and X-Bus 124 chooses addresses within the selected BIOS image.
A limitation of system 200 relates to the possible inconsistency due to the non-standardized access to the BIOS by CPU 108 and BMC 140. It is therefore difficult to arbitrate BIOS selection between CPU 108 and BMC 140.
Related art systems include U.S. Pat. No. 6,282,642 to Cromer et al, describing a computer system which can be pre-set over a network to boot to a first or second remote boot protocol prior to being powered on over the network. The system is coupled to a remote computer via a data communication link. The system includes a communication subsystem for communicating data with the computer system. The communication subsystem is supplied with auxiliary power and is operative to communicate with the computer system regardless of whether the computer system is in a normal operating state. The remote computer includes a program for sending a first packet to the computer system via the communication link. The first packet contains a boot parameter which is indicative of the first or second remote boot protocol. The computer system is operative to receive the first packet via the communication subsystem and store the boot parameter in a memory thereof without powering on. The memory is accessed by BIOS during a network boot sequence and the system will boot in accordance with the specified boot protocol stored in the memory.
Another related art system includes U.S. Pat. No. 6,282,643 also to Cromer et al., disclosing a personal computer system which includes a central processing unit (CPU) coupled to a direct access storage device (DASD), a random access memory (RAM), and a LAN controller. A flash memory module is coupled to the CPU and an input/output (IO) bus and includes a basic input/output system (BIOS) stored therein. The BIOS is effective for responding to the energization of the computer system by initiating a power on self test (POST). The BIOS is further operative on completion of the POST for transferring a portion of BIOS from the module to the RAM and for transferring control of the computer system to the BIOS portion. The portion of BIOS is operative to load a protected mode operating system (OS) into RAM and transfer control to the OS. The system further includes a logic circuit coupled to the flash memory and the IO bus. A communication subsystem is coupled to the IO bus, the logic circuit and the flash memory for allowing the remote computer to access the BIOS in flash memory while the protected mode OS is running.
What is needed in the art is a system and method for improved management of more than one BIOS image.